Data is digitally stored in semiconductor memory devices. These semiconductor memory devices fall into one of two categories. Volatile memory devices retain their data only when they are powered on; whereas, non-volatile memory chips can retain the data even if no external power is being supplied to the memory device. One popular form of nonvolatile memory device is flash memory. Flash memory is versatile because it can be erased and programmed multiple times. Furthermore, flash memory is relatively inexpensive compared to other types of non-volatile memory devices. Consequently, flash memory is ideal for applications that demand significant amounts of non-volatile, solid-state storage. Examples of applications employing flash memory include USB flash drives, digital audio players, digital cameras and camcorders, mobile phones, automotive control systems, gaming consoles, etc.
Flash memory is typically made up of an array of floating gate transistors, commonly referred to as memory “cells.” One or more bits of data are stored as charge by each memory cell. For example, dual bit memory devices use a silicon-oxide-nitride-oxide-silicon (SONOS) type architecture in which a lower layer of silicon oxide is formed over a semiconductor substrate that is typically silicon. A layer of silicon nitride is formed on the lower layer of silicon oxide, an upper layer of silicon oxide is formed on the layer of silicon nitride and a layer of an electrically conductive material is formed on the upper layer of silicon oxide. The combination of the lower silicon oxide layer, the silicon nitride layer, and the upper silicon oxide layer are capable of trapping charge and are commonly referred to as a charge trapping dielectric structure or layer. It should be noted that the charge trapping structure is defined as a stack of ONO. When more than one bit of information is stored in the charge trapping structure, the memory device is referred to as a dual bit memory device. Bit lines are typically formed in the portion of the semiconductor substrate that is below the charge trapping structure and word lines may be formed from the layer of electrically conductive material that is disposed on the charge trapping structure. In a dual bit memory device, two bits are stored per cell by biasing the bit line, the word line, the source, and the drain of the memory cell such that a bit and a complementary bit are stored. This arrangement enables flash memory cells to be manufactured efficiently and economically.
FIG. 1 shows a conventional memory cell. In a conventional flash memory fabrication process, the tunnel oxide, the charge-trapping layer, and top charge block oxide 101 (e.g., oxide-nitride-oxide ONO layer) and one or more polysilicon layers 102 are formed before the shallow trench isolation (STI 103) definition. It should be noted that the nitride layer can be comprised of nitride, silicon rich nitride, a combination of nitride on top of silicon rich nitride or multiple layers with different percentages of silicon content. After the STI 103 formation, another polysilicon layer can be deposited on the previous polysilicon layer. Subsequently, the word line is defined. Unfortunately, this conventional approach produces sharp corners 104-105 because the nature of the STI process produces near vertical sides. These sharp corners directly contribute to device degradation in performance and reliability. Simply going back and rounding off the sharp corners cannot solve these associated problems due to the increase in oxide encroachment which detrimentally impacts the erase and programming of the memory cell. Furthermore, rounding off the sharp corners would reduce the core cell current by a smaller effective channel width, which is highly undesirable.
Furthermore, various semiconductor fabrication processes use masks to help align the memory cells. Aligning the cells produces a more organized and compact design. Although masking techniques properly align the cells, scaling becomes an issue. It becomes harder to place the cells closer together. It is important to place the cells as close together without impacting their functionality because denser cells can hold more data for a given semiconductor area. In other words, tighter tolerances allow for greater memory capacity at reduced cost.